The present application relates to time-to-digital converters with built in self-test (BIST), corresponding to methods and apparatuses comprising such time-to-digital converters.
Time-to-digital converters (TDCs) are devices which measure a length of a time period and output the length of the time period as a digital value. Time-to-digital converters may, for example, be employed in a phase-locked loop. For instance, a time-to-digital converter may be employed to measure a time difference between edges, such as rising edges, of a reference signal or a feedback signal in a phase-locked loop. However, time-to-digital converters are not limited to such applications. Other example applications for time-to-digital converters include TDC-based analog-to-digital converters, and the like.
In some implementations, a time-to-digital converter may comprise an asynchronously timed core and a digital periphery. Such a core may be somewhat difficult to test during production, because of characteristics which may be desired for test signals to be input to the time-to-digital converter. For example, time-to-digital converters often have an inherently asynchronous internal structure. Time-to-digital converters may generally comprise at least one delay line including multiple delay elements which may, for example, be configured in a loop. A start signal to start the time-to-digital converter making a time measurement may propagate along the delay line in a self-controlled way, wherein the propagation velocity may depend on the combined delay of the delay elements of the delay line. Therefore, it may not be possible to force the delay line, and therefore, force the inputs to comparators of the time-to-digital converter that are coupled to the delay line, into a static state, which is generally used for testing logic circuits.